Updated transceiver data rate from 25 Gbps to 17.4 Gbps for GXT selection in Transceiver Channel Typeparameter.Added SerialLite III Streaming Intel FPGA IP Core Design Examples section.Reorganized SerialLite III Streaming IP Core Functional Description and SerialLite III Streaming IP Core Clocking Guidelines chapters.Updated resources for 28 Gbps with 4 data lanes in SerialLite III Streaming IP Core Performance and Resource Utilization table.Updated 28 Gbps with 4 data lanes support for Intel® Stratix® 10 devices.Added IP core link up sequences with waveforms in Link-Up Sequence topic.Updated reset scheme for Intel® Stratix® 10 E-tile transceiver devices.Added Intel® Stratix® 10 E-tile transceiver devices standard and advanced clocking mode block diagrams.Updated core latency for Intel® Stratix® 10 E-tile transceiver devices in Latency Measurement for Duplex Core table.Updated Error Detection, Reporting, and Recovering Mechanism topic with reporting and recovering mechanisms.Added a note to clarify that Riviera Pro is not supported for E-tile transceiver.RX Adaptation FIFO Overflow Enable bit 7 of RX Error Interrupt Enable Register.RX Data Error Enable bit 11 of RX Error Interrupt Enable Register.RX Adaptation FIFO Overflow bit 7 of RX Error Status Register.RX Data Error bit 11 of RX Error Status Register.Added the following bits in Sink Configuration and Status Registers for MAC table:.RX Loss of Frame Lock Interrupt bit 2 of RX Error Interrupt Enable Register.RX Loss of Frame Lock Consolidated Status bit 2 of RX Error Status Register.Removed the following bits in Sink Configuration and Status Registers for MAC table:.Added the following registers in Source Configuration and Status Registers for MAC and Sink Configuration and Status Registers for MAC tables:.Added note to clarify parameters that are not supported in E-tile transceiver.Added Serial Lite III Streaming Intel FPGA IP Transceiver Tiles Support in Intel Stratix 10 Devices table.Updated resource utilization with E-tile transceiver support.Updated phy_mgmt_addr signal description for Intel® Stratix® 10 device in L-Tile/H-Tile/E-Tile Transceiver Native PHY Intel® Stratix® 10 IP Core Signals (Interlaken Mode) table. Avalon-ST interface to Avalon streaming interfaceĪdded Intel® Stratix® 10 E-Tile Transceiver PHY User Guide: PMA Adaptation link in the Parameter Settings for Intel® Stratix® 10 Devices topic, to provide more information on parameters in the PMA Adaptation tab.Avalon-MM interface to Avalon memory-mapped interface.Added Serial Lite III Streaming IP latency values for standard and advanced modes in 28 Gbps transceiver rate.Rephrased Transceiver Native PHY Intel® Arria® 10/ Intel® Cyclone® 10 GX FPGA Intel IP core to Transceiver Native PHY IP for Intel® Arria® 10 devices.Made editorial edits throughout the document.Added information for interface_clock_reset_tx. Updated clock domain and description for interface_clock_reset_rx.Updated Table: Serial Lite III Streaming Duplex Core Signals for Intel® Stratix® 10 L-tile, H-tile, and E-tile Devices:.Renamed the document title to Serial Lite III Streaming Intel® FPGA IP User Guide.Updated the description for the ready_tx and ready_rx signals in Table: Serial Lite III Streaming Duplex Core Signals for Intel® Stratix® 10 L-tile, H-tile, and E-tile Devices.Table: Serial Lite III Streaming Sink Core Signals for Intel® Stratix® 10 L-tile and H-tile Devices.Table: Serial Lite III Streaming Source Core Signals for Intel® Stratix® 10 L-tile and H-tile Devices.Updated the description for the ready signal in the following tables:.Updated the device family support for Table: Serial Lite III Streaming Intel® FPGA IP.Removed references to NCSim simulator throughout the document.Added support for QuestaSim* simulator.
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